1. Field of the Invention
The invention relates to a method for fabricating a flash memory, and more particularly, to a method for fabricating a split-gate flash memory.
2. Description of the Related Art
At present, nonvolatile memory is widely used in the whole range of electrical devices. In particular, programmable nonvolatile memory having a flash memory structure such as the erasable programmable read-only memory and electrically erased programmable read-only memory has attracted immense interest. In general, a flash memory comprises two gates, a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate while the control gate is connected to a word line.
FIG. 1 is a schematic, cross-sectional view showing a structure of a split-gate flash memory according to the prior art. In the FIG. 1, a floating gate 102 and a control gate 104 are formed on a substrate 100. A split-gate oxide layer 106 and a dielectric layer 108 separate the floating gate 102 and the control gate 104. Source/drain regions 110a, 110b are respectively formed in the substrate 100 adjacent to the collective structure of the control gate 104 and the floating gate 102. Sometimes, the control gate 104 is referred to as a selective gate. Referring to FIG. 1, the semiconductor process is first to form the floating gate 102 on the substrate 100 and then to form the split-gate oxide layer 106. Subsequently, a conductive layer is formed on the split-gate oxide layer 106. Then, the conductive layer is defined into the control gate 104 as shown in FIG. 1 by photolithography and etching. Afterwards, an ion implantation process is performed to form the source/drain regions 110a, 110b. A distance L.sub.1 covered by the control gate 104 between the source/drain region 110a and the structure comprising the dielectric layer 108 and the floating gate 102 is referred to as a channel length of the selective gate.
According to the prior art, the process is first to form the control gate 104 and then to form the source/drain region 110a; thus, the channel length L.sub.1 of the selective gate depends on the accuracy of photolithography for defining the control gate 104. Thus, when the photomask used for defining the control gate 104 is misaligned and the control gate 104 formed is shifted from a desired position, the channel length L.sub.1 is increased or decreased, and the reading current and the programming current are varied with the length L.sub.1. When the length L.sub.1 is increased, the reading current is reduced; thus, a sensitive sense amplifier is required for detecting the reading current. In addition, the programming current is also reduced while the length L.sub.1 is increased; thus, the time for programming is increased, the speed becomes slower, and the operation time is increased.